module RF (
    input logic         clk,
    input logic         reset,
    input logic         WB_RFWr_End,
    input logic [4:0]   RA,
    input logic [4:0]   RB,
    input logic [4:0]   RW,
    input logic [31:0]  DataWr,
    output logic [31:0] DataOut1,
    output logic [31:0] DataOut2
);
    logic [31:0][31:0] RF;

    assign DataOut1 = ((RA == RW) && (RW != 5'b0)) ? DataWr : RF[RA];
    assign DataOut2 = ((RB == RW) && (RW != 5'b0)) ? DataWr : RF[RB];

    always_ff @(posedge clk or negedge reset) begin
        if(!reset) begin
            RF <= '0;
        end
        else if(WB_RFWr_End) begin
            RF[RW] <= DataWr;
        //    $display("$%d<-0x%8X", RW, DataWr);
        end
    end
endmodule